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SI9122 Vishay Siliconix 500-kHz Half-Bridge DC-DC Converter With Integrated Secondary Synchronous Rectification Drivers FEATURES D 12-V to 72-V Input Voltage Range D Compatible with ETSI 300 132-2 D Integrated Half Bridge Primary Drivers (1-A Drive Capability) D Secondary Synchronous Signals With Programmable Deadtime Delay D Voltage Mode Control D Voltage Feedforward Compensation D High Voltage Pre-Regulator Operates During Start-Up D Current Sensing On Low-Side Primary Device D Frequency Foldback Eliminates Constant Current Tail D Advanced Maximum Current Control During Start-Up and Shorted Load D Low Input Voltage Detection D Programmable Soft-Start Function D Over Temperature Protection APPLICATIONS D Network Cards D Power Supply Modules DESCRIPTION SI9122 is a dedicated half-bridge IC ideally suited to fixed telecom applications where efficiency is required at low output voltages (e.g. <3.3 V). Designed to operate within the fixed telecom voltage range of 33-72 V and withstand 100 V, 100 ms transients, the IC is capable of controlling and driving both the low and high-side switching devices of a half bridge circuit and also controlling the switching devices on the secondary side of the bridge. Due to the very low on-resistance of the secondary MOSFETs, a significant increase in the efficiency can be achieved as compared with conventional Schottky diodes. Control of the secondary devices is by means of a pulse transformer and a pair of inverters. Such a system has efficiencies well in excess of 90% even for low output voltages. On-chip control of the dead time delays between the primary and secondary synchronous signals keep efficiencies high and prevent accidental destruction of the power transformer. An external resistor sets the switching frequency from 200 kHz to 600 kHz. SI9122 has advanced current monitoring and control circuitry which allow the user to set the maximum current in the primary circuit. Such a feature acts as protection against output shorting and also provides constant current into large capacitive loads during start-up or when paralleling power supplies. Current sensing is by means of a sense resistor on the low-side primary device. FUNCTIONAL BLOCK DIAGRAM VIN D1 BST VCC CVCC EP Voltage Information Voltage Control PWM CS2 Current Control CS1 RBBM Current Sense Timer BBM Secondary Drivers SRH Half-Bridge Synchronous Controller Primary Drivers t DL (Low) RS Pulse Transformer CLOAD Pre-Reg CBOOST LX DH (High) VOUT RLOAD + CVIN1 - Power Transformer To VCC SI9122 SRL Opto Error Amp 1.215 V Figure 1. Document Number: 71815 S-41944--Rev. F, 18-Oct-04 www.vishay.com 1 SI9122 Vishay Siliconix TECHNICAL DESCRIPTION SI9122 is a voltage mode controller for the half-bridge topology. With 100-V depletion mode MOSFET capability, the SI9122 is capable of powering directly from the high voltage bus to VCC through an external PNP pass transistor, or may be powered through an external regulator directly through the VCC pin. With PWM control, SI9122 provides peak efficiency throughout the entire line and load range. In order to simplify the traditional secondary synchronous rectification, SI9122 provides intelligent gate drive signals to control the secondary MOSFETs. With independent gate drive signals from the controller, transformer design is no longer limited by the gate to a source rating of the MOSFETs. SI9122 provides constant VGS voltage, independent of line voltage to minimize the gate charge loss as well as conduction loss. A break-before-make function is included to prevent shoot through current or transformer shorting. Adjustable Break-Before-Make time is incorporated into the IC and is programmable by an external resistor value. SI9122 is packaged in TSSOP-20 and MLP65-20 packages. In TSSOP-20 packaging, both standard and lead (Pb)-free options are available. The MLP65-20 package is lead (Pb)-free. In order to satisfy the stringent ambient temperature requirements, SI9122 is rated to handle the industrial temperature range of -40 to 85_C. When a situation arises which results in a rapid increase in primary (or secondary current) such as output shorted or start-up with a large output capacitor, control of the PWM generator is handed over to the the current loop. Monitoring of the load current is by means of a sense resistor on the primary low-side switch. DETAILED BLOCK DIAGRAM VIN VCC ROSC High-Side Primary Driver REG_COMP Pre-Regulator VREF 9.1 V + - VUVLO BST Int DH LX 8.8 V VFF OSC Ramp VINDET VREF 132 kW 60 kW EP Error Amplifier - + V REF 2 + - + - VUV VSD 550 mV + - PWM Comparator Low-Side Driver VCC DL PGND Driver Control and Timing OTP VCC SRH SYNC Driver High VCC 20 mA SS ISS 8V + - Peak DET Duty Cycle Control CS2 CS1 SRL SYNC Driver Low Over Current Protection GND CL_CONT BBM SI9122 Figure 2. www.vishay.com Document Number: 71815 S-41944--Rev. F, 18-Oct-04 2 SI9122 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V) VIN (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V VIN (100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 V VBST (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 V (100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 V VLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V VBST - VLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VREF, ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa TSSOP-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 mW MLP65-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500 mW Thermal Impedance (QJA) TSSOP-20b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75_C/W MLP65-20c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38_C/W Notes a. Device mounted on JEDEC compliant 1S2P test board.. b. Derate -14 mW/_C above 25_C. c. Derate -26 mW/_C above 25_C. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V) VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 to 72 V CVIN1 o CVIN2 . . . . . . . . . . . . . . . . . . . . . . . . . 100 mF/ESR v 100 mW, 0.1 mF VCC Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 to 13.2 V CVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 mF fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 600 kHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 to 72 kW RBBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 to 50 kW CBBMh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >680 pF CSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 nF CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF CBOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF CLOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mF Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 2 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC Reference Voltage Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 mA SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Reference (3.3 V) Output Voltage Short Circuit Current Load Regulation Power Supply Rejection VREF ISREF dVr/dlr PSRR VCC = 12 V, 25_C Load = 0 mA VREF = 0 V IREF = 0 to -2.5 mA @ 100Hz -30 60 3.2 3.3 3.4 -50 -75 V mA mV dB Limits -40 to 85_C Symbol fNOM = 500 kHz, VIN = 72 V kH VINDET = 7.2 V; 10 V v VCC v 13.2 V Minb Typc Maxb Unit Oscillator Accuracy (1% ROSC) Max Frequency Foldback Frequencyd FMAX FFOBK ROSC = 30 kW, fNOM = 500 kHz ROSC = 24 kW fNOM = 500 kHz, VCS2 - VCS1 u 150 mV -20 600 100 20 % kHz Error Amplifier Input Bias Current Gain Bandwidth Power Supply Rejection Slew Rate IBIAS AV BW PSRR SR @ 100Hz VEP = 0 V -40 -2.2 5 60 0.5 -15 mA V/V MHz dB V/ms Current Sense Amplifier Input Voltage CM Range Input Amplifier Gain Input Amplifier Bandwidth Document Number: 71815 S-41944--Rev. F, 18-Oct-04 VCM AVOL BW VCS1 - GND, VCS2 - GND "150 17.5 5 mV dB MHz www.vishay.com 3 SI9122 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Current Sense Amplifier Input amplifier Offset Voltage CL_CONT Current Lower Current Limit Threshold Upper Current Limit Threshold Hysteresis CL_CONT Clamp Level CL_CONT(min) VOS dVCS = 0 ICL_CONT VTLCL VTHCL dVCS = 100 mV dVCS = 170 mV IPD = IPU - ICL_CONT = 0 See Figure 6 IPD u 2 mA IPU t 500 mA IPU = 500 mA 0.6 "5 120 0 u2 100 150 -50 1.5 V mV V mV mA mA Limits -40 to 85_C Symbol fNOM = 500 kHz, VIN = 72 V VINDET = 7.2 V; 10 V v VCC v 13.2 V Minb Typc Maxb Unit PWM Operation DMAX Duty Cyclee yy DMIN fOSC = 500 kHz VEP= 0 V VEP= 1.75 V 90 92 t15 3 95 % VCS2 - VCS1 u 150 mV Pre-Regulator Input Voltage Input Leakage Current Regulator Bias Current Regulator_Comp Regulator Comp Pre-Regulator Drive Capacility VCC P R Pre-Regulator T l t Turn Off Threshold Voltage Undervoltage Lockout VUVLO Hysteresisg +VIN ILKG IREG1 IREG2 ISOURCE ISINK ISTART VREG1 VREG2 VUVLO VUVLOHYS IIN = 10 mA VIN = 72 V, VCC u VREG VIN = 72 V, VINDET t VSD VIN = 72 V, VINDET u VREF VCC = 12 V VCC t VREG VINDET u VREF VINDET = 0 V VCC Rising 7.15 TA = 25_C 8.1 TA = 25_C -29 50 20 7.4 8.5 9.1 9.1 9.2 8.8 8.8 0.5 9.8 9.3 10.4 9.7 V 86 8 -19 82 72 10 200 14 -9 110 V mA mA mA mA Soft-Start Soft-Start Current Output Soft-Start Completion Voltage ISS VSS_COMP Start-Up Condition Normal Operation 12 7.35 20 8.05 28 8.85 mA V Shutdown VINDET Shutdown FN VINDET Hysteresis VSD VINDET Rising VINDET 350 550 200 720 mV VINDET Input Threshold Voltages VINDET - VIN Under Voltage VINDET Hysteresis VUV VINDET Rising VINDET 3.13 3.3 0.3 3.46 V Over Temperature Protection Activating Temperature De-Activating Temperature TJ Increasing TJ Decreasing 160 130 _C Converter Supply Current (VCC) Shutdown Switching Disabled Switching w/o Load Switching with CLOAD ICC1 ICC2 ICC3 ICC4 Shutdown, VINDET = 0 V VINDET t VREF VINDET u VREF, fNOM = 500 kHz VCC = 12 V, CDH = CDL = 3 nF CSRH = CSRL = 0.3 nF 50 4 5 8 10 21 350 12 14 mA mA www.vishay.com 4 Document Number: 71815 S-41944--Rev. F, 18-Oct-04 SI9122 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Output High Voltage Output Low Voltage Boost Current LX Current Peak Output Source Peak Output Sink Rise Time Fall Time Limits -40 to 85_C Symbol VOH VOL IBST ILX ISOURCE ISINK tr tf fNOM = 500 kHz, VIN = 72 V VINDET = 7.2 V; 10 V v VCC v 13.2 V Minb VBST - 0.3 Typc Maxb Unit Output MOSFET DH Driver (High-Side) Sourcing 10 mA Sinking 10 mA VLX = 72 V, VBST = VLX + VCC VLX = 72 V, VBST = VLX + VCC VCC = 10 V CDH = 3 nF 1.3 -1.1 0.75 1.9 -0.7 -1.0 1.0 35 35 VLX + 0.3 2.7 -0.4 -0.75 V mA A ns Output MOSFET DLDriver (Low-Side) Output High Voltage Output Low Voltage Peak Output Source Peak Output Sink Rise Time Fall Time VOH VOL ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA VCC = 10 V CDL = 3 nF -1.0 0.75 1.0 35 35 VCC - 0.3 0.3 -0.75 V A ns Synchronous Rectifier (SRH, SRL) Drivers Output High Voltage Output Low Voltage VOH VOL tBBM1 Break-Before-Make Break Before Make Timef tBBM2 tBBM3 tBBM4 Peak Output Source Peak Output Sink Rise Time Fall Time ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA TA = 25_C RBBM = 33 kW See Figure 3 25_C, kW, TA = 25_C RBBM = 33 kW LX = 72 V 25_C,R kW, VCC = 10 V CSRH = CSRL = 0 3 nF 0.3 55 40 35 55 -100 100 35 35 mA ns ns VCC - 0.4 0.4 V Voltage Mode Error Amplifier td1DH td2DL Input to high-side switch off Input to low-side switch off t200 t200 ns Current Mode Current Amplifier td3DH td4DL Input to high-side switch off Input to low-side switch off t200 t200 ns Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (-40_ to 85_C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. FMIN when VCL_CONT at clamp level. Typical foldback frequency change +20%, -30% over temperature. e. Measured on SRL or SRH outputs. f. See Figure 3 for Break-Before-Make time definition. g. VUVLO tracks VREG1 by a diode drop h. CBBM may be required to reduce noise into BBM pin for non-optimum layout. Document Number: 71815 S-41944--Rev. F, 18-Oct-04 www.vishay.com 5 SI9122 Vishay Siliconix TIMING DIAGRAM FOR MOS DRIVERS VCC GND VCC DL GND VCC SRL SRL DL PWM PWM PWM PWM GND VBST VMID DH DH DH GND DH VCC GND SRH SRH Time DH 50% V LX LX tBBM1 tBBM2 tBBM3 tBBM4 BST = LX + VCC DH, LX DH, LX VMID SRH DH, LX 50% VCC GND SRL DL tBBM3 SRL tBBM4 VCC GND Return to: Specification Table Rectification Timing Sequence Primary MOSFET Drivers Secondary MOSFET Drivers tBBM1 tBBM2 Figure 3. www.vishay.com 6 Document Number: 71815 S-41944--Rev. F, 18-Oct-04 SI9122 Vishay Siliconix PIN CONFIGURATION SI9122DQ (TSSOP-20) VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 1 2 3 4 5 6 7 8 9 10 Top View Top View 20 19 18 17 16 15 14 13 12 11 BST DH LX DL PGND SRH SRL SS BBM CL_CONT VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SI9122DLP (MLP65-20) BST DH LX DL PGND SRH SRL SS BBM CL_CONT ORDERING INFORMATION Standard Part Number SI9122DQ-T1 Lead (Pb)-Free Part Number SI9122DQ-T1--E3 SI9122DLP-T1--E3 Temperature Range -40 to 85_C 40 Package TSSOP-20 MLP65-20 Eval Kit SI9122DB Issue 3 Temperature Range -10 to 70_C Board Type Surface Mount and Thru-Hole PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Document Number: 71815 S-41944--Rev. F, 18-Oct-04 Name VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 CL_CONT BBM SS SRL SRH PGND DL LX DH BST Input supply voltage for the start-up circuit. Control signal for an external pass transistor. Supply voltage for internal circuitry 3.3-V reference, decoupled with 1-mF capacitor Ground External resistor connection to oscillator Voltage control input Function VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET falls below preset threshold voltages and provides the feed forward voltage. Current limit amplifier negative input Current limit amplifier positive input Current limit compensation Programmable Break-Before-Make time connection to an external resistor to set time delay Soft-Start control - external capacitor connection Signal transformer drive, sequenced with the primary side. Signal transformer drive, sequenced with the primary side. Power ground. Low-side gate drive signal - primary High-side source and transformer connection node High-side gate drive signal - primary Bootstrap voltage to drive the high-side n-channel MOSFET switch www.vishay.com 7 SI9122 Vishay Siliconix VCC VIN Pre-Regulator Bandgap Reference 3.3 V + - VINDET CL_CONT VREF + - VSD 160_C Temp Protection VSD Clock Clock 132 kW 60 kW EP - + VREF/2 - + PWM Generator Timer VCC Logic PGND Logic VUV VUVLO OTP VCC Low-Side Driver DL High Voltage Interface VREG 9.1 V VREF + - VUVLO 9.1 V VUV + - 8.6 V High-Side Primary Driver BST DH LX Voltage Feedforward Frequency Foldback 550 mV ROSC Oscillator OSC CS2 CS1 Current Control + - 100 mV Gain Loop Control Blanking Synchronous Driver (High) SRH VCC CL_CONT VCC 8V 20 mA GND BBM Synchronous Driver (Low) SRL SI9122 Soft-Start SS Enable SS Figure 4. Detailed Functional Block DETAILED OPERATION Start-Up When VINEXT rises above 0 V, the internal pre-regulator begins to charge up the Vcc capacitor. Current into the external VCC capacitor is limited to typically 40 mA by the internal DMOS device. When Vcc exceeds the UVLO voltage of 8.8 V a soft-start cycle of the switch mode supply is initiated. The VCC supply continues to be charged by the pre-regulator until VCC equals Vreg. During this period, between VUVLO and VREG, excessive load current will result in VCC falling below VUVLO and stopping switch mode operation. This situation is avoided by the hysteresis between VREG and VUVLO and correct sizing www.vishay.com of the VCC capacitor, bootstrap capacitor and the soft-start capacitor. The value of the VCC capacitor should therefore be chosen to be capable of maintaining switch mode operation until the VCC can be supplied from the external circuit (e.g via a power transformer winding and zener regulator). Feedback from the output of the switch mode supply charges VCC above VREG and fully disconnects the pre-regulator, isolating VCC from VIN. VCC is then maintained above VREG for the duration of switch mode operation. In the event of an over voltage condition on VCC, an internal voltage clamp turns on at 14.5 V to shunt excessive current to GND. Document Number: 71815 S-41944--Rev. F, 18-Oct-04 8 SI9122 Vishay Siliconix Care needs to be taken if there is a delay prior to the external circuit feeding back to the VCC supply. To prevent excessive power dissipation within the IC it is advisable to use an external PNP device. A pin has been incorporated on the IC, (REG_COMP) to provide compensation when employing the external device. In this case the VIN pin is connected to the base of the PNP device and controls the current, while the REG_COMP pin determines the frequency compensation of the circuit. To understand the operation please refer to Figure 5. The soft-start circuit is designed for the dc-dc converter to start-up in an orderly manner and reduce component stress on the IC. This feature is programmable by selecting an external CSS. An internal 20-mA current source charges CSS from 0 V to the final clamped voltage of 8 V. In the event of UVLO or shutdown, VSS will be held low (<1 V) disabling driver switching. To prevent oscillations, a longer soft-start time may be needed for high capacitive loads and high peak output current applications. Reference The reference voltage of SI9122 is set at 3.3 V. The reference voltage is de-coupled externally with 0.1-mF capacitor. The VREF voltage is 0 V in shutdown mode and has 50-mA source capability. Voltage Mode PWM Operation Under normal load conditions, the IC operates in voltage mode and generates a fixed frequency pulse width modulated signal to the drivers. Duty cycle is controlled over a wide range to maintain output voltage under line and load variation. Voltage feed forward is also included to take account of variations in supply voltage VIN. In the half-bridge topology requiring isolation between output and input, the reference voltage and error amplifier must be supplied externally, usually on the secondary side. The error information is thus passed to the power controller through an opto-coupling device. This information is inverted, hence 0 V represents the maximum duty cycle, whilst 2 V represents minimum duty cycle. The error information enters the IC via pin EP, and is passed to the PWM generator via an inverting amplifier. The relationship between Duty cycle and VEP is shown in the Typical Characteristic Graph,Duty Cycle vs. VEP 25_C , page 19. Voltage feedforward is implemented by taking the attenuated VIN signal at VINDET and directly modulating the duty cycle. The relationship between Duty cycle and VINDET is shown in the the Typical Characteristic Graph, Duty Cycle vs. VINDET, page 16. At start-up, i.e., once VCC is greater than VUVLO, switching is initiated under soft-start control which increases primary switch on-times linearly from DMIN to DMAX over the soft-start period. Start-up from a VINDET power down is also initiated under soft-start control. Half-Bridge and Synchronous Rectification Timing Sequence The PWM signal generated within the SI9122 controls the low and high-side bridge drivers on alternative cycles. A period of Document Number: 71815 S-41944--Rev. F, 18-Oct-04 inactivity always results after initiation of the soft-start cycle until the soft-start voltage reaches approximately 1.2 V and PWM controlled switching begins. The first bridge driver to switch is always the low-side, DL as this allows charging of the high-side boost capacitor. The timing and coordination of the drives to the primary and secondary stages is very important and shown in Figure 3. It is essential to avoid the situation where both of the secondary MOSFETs are on when either the high or the low-side switch are active. In this situation the transformer would effectively be presented with a short across the output. To avoid this, a dedicated break-before-make circuit is included which will generate non overlapping waveforms for the primary and the secondary drive signals. This is achieved by a programmable timer which delays the switching on of the primary driver relative to the switching off of the related secondary and subsequently delays the switching on of the secondary relative to the switching off of the related primary. Typical variation in the tBBM3 and tBBM4 delay with LX voltage is shown in graphs tBBM3, tBBM4 and for RBBM = 33 kW. This is due to a reduction in propagation delay through the high-side driver path as the LX voltage increases and must be considered in setting the delay for the system level design. Variation of BBM time with RBBM is shown in graph tBBM1 to tBBM4 vs. RBBM. Primary High- and Low-Side MOSFET Drivers The drive voltage for the low-side MOSFET switch is provided directly from VCC. The high-side MOSFET however requires the gate voltage to be enhanced above VIN. This is achieved by bootstraping the VCC voltage onto the LX voltage (the high-side MOSFET source). In order to provide the bootstrapping an external diode and capacitor are required as shown on the application schematic. The capacitor will charge up after the low-side driver has turned on. The switch gate drive signals DH and DL are shown in Figure 3. Secondary MOSFET Drivers The secondary side MOSFETs are driven from the SI9122 via a center tapped pulse transformer and inverter drivers. The waveforms from the IC SRH and SRL are shown in Figure 3. Of importance is the relative voltage between SRH and SRL, i.e. that which is presented across the primary of the pulse transformer. When both potentials of SRL and SRH are equal then by the action of the inverting driver both secondary MOSFETs are left on. Oscillator The oscillator is designed to operate at a nominal frequency of 500 kHz. The 500-kHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. The oscillator and therefore the switching frequency is programmable by attaching a resistor to the ROSC pin. Under overload conditions the oscillator frequency is reduced by the current overload protection to enable a constant current to be maintained into a low impedance circuit. www.vishay.com 9 SI9122 Vishay Siliconix Current Limit Current mode control providing constant current operation is achieved by monitoring the differential voltage between the CS1and CS2 pins which are connected across a primary low-side sense resistor. Once this differential voltage exceeds the 100-mV trigger point, the voltage on the CL_CONT pin is pulled lower at a rate proportional to the excess voltage and the value of the external capacitor connected between the CL_CONT pin and ground. If the voltage between CS1 and CS2 exceeds 150 mV the CL_CONT capacitor is discharged rapidly resulting in minimum duty cycle and frequency immediately. Lowering the CL_CONT voltage results in PWM control of the output drive being taken over by the current limit control loop. Current control works to initially reduce the switching duty cycle down to DMIN (12.5%). Further reduction in the duty cycle is accompanied by a reduction in switching frequency at a rate proportional to the duty cycle. This prevents the on time of the primary drivers fnom from reducing below 100 ns and avoiding a current tail. Frequency reduction occurs to a maximum of one fifth of the nominal frequency. With constant current mode control of on time and with reduced operating frequency, protection of the MOSFET switches is increased during fault conditions. Minimum duty cycle and reduced frequency switching continues for the duration of the fault condition. The converter reverts to voltage mode operation immediately whenever the primary current fails to reach the limit level. CL_CONT clamps to 6.5 V when not in current limit. The soft-start function does not apply under current limit as this would constitute hiccup mode operation. VIN Voltage Monitor -VINDET The chip provides a means of sensing the voltage of VIN, and withholding operation of the output drivers until a minimum voltage of VREF (3.3 V, 300-mV hysteresis), is achieved. This VCC IPU 120 mA (nom) GM AV OSC VREF is achieved by choosing an appropriate resistive tap between the ground and VIN, and comparing this voltage with the reference voltage. When the applied voltage is greater than VREF, the output drivers are activated as normal. VINDET also provides the input to the voltage feed forward function. However, if the divided voltage applied to the VINDET pin is greater than VCC -0.3 V, the high-side driver, DH, will stop switching until the voltage drops below VCC -0.3 V. Thus, the resistive tap on the VIN divider must be set to accommodate the normal VCC operating voltage to avoid this condition. Alternatively, a zener clamp diode from VINDET to GND may also be used. Shutdown Mode If VINDET is forced below the lower threshold, a minimum of 350 mV(VSD), the device will enter SHUTDOWN mode. This powers down all unnecessary functions of the controller, ensures that the primary switches are off and results in a low level current demand from the VIN or VCC supplies. VINEXT REXT VIN (SI9122) HVDMOS VCC REG_COMP CEXT 2 nF CVCC 0.5 mF GND PNP Ext Auxillary VCC 14.5 V Figure 5. High-Voltage Pre-Regulator Circuit + Peak Detect - VOFFSET CL_CLAMP CL_CONT CS1 CS2 Blank - + AV AV 150 mV REXT + - AV 100 mV GM IPD 0 - 240 mA (nom) CEXT Figure 6 . Current Limit Circuit www.vishay.com 10 Document Number: 71815 S-41944--Rev. F, 18-Oct-04 SI9122 Vishay Siliconix TYPICAL CHARACTERISTICS FOSC vs. ROSC @ VCC = 12 V 600 3.300 3.295 500 3.290 FOSC (kHz) 400 V REF (V) 3.285 3.280 300 3.275 200 20 30 40 50 ROSC (kW) 60 70 80 3.270 -50 VREF vs. Temperature, VCC = 12 V -25 0 25 50 75 100 Temperature (_C) 10.0 VREG vs. Temperature, VIN = 48 V 100 90 SRL, SRH Duty Cycle vs. VEP 9.5 Duty Cycle (%) 80 70 60 50 40 30 VCC = 12 V 7.2 V 3.6 V = VINDET 4.8 V V REG(V) 9.0 VINDET u VREF 8.5 TC = -11 mV/C 8.0 20 10 7.5 -50 -25 0 25 50 75 100 125 150 0 0.0 0.5 1.0 VEP (V) 1.5 2.0 Temperature (_C) ISS vs. Temperature 25 VCC = 13 V 8.20 8.15 VSS vs. Temperature, VCC = 12 V 23 TC = +1.25 mV/C VCC = 12 V V SS (V) 8.10 8.05 8.00 VINDET u VREF I SS1 (uA) 21 19 VCC = 10 V 17 7.95 7.90 -50 15 -50 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 150 Temperature (_C) Document Number: 71815 S-41944--Rev. F, 18-Oct-04 Temperature (_C) www.vishay.com 11 SI9122 Vishay Siliconix TYPICAL CHARACTERISTICS IREG2 vs. Temperature 11 10 9 IREG2 (mA) 8 7 6 5 -50 ICC3 (mA) 13 12 11 10 9 8 7 -50 ICC3 vs. Temperature -25 0 25 50 75 100 -25 0 25 50 75 100 Temperature (_C) Temperature (_C) DH, DL ISOURCE vs. VOH 250 250 DH, DL ISINK vs. VOL 200 VCC = 12 V 200 VCC = 12 V ISOURCE (mA) ISINK (mA) 150 150 100 100 50 50 0 0 200 400 VOH (mV) 600 800 0 0 200 400 VOL (mV) 600 800 35 30 SRL, SRH ISOURCE vs. VOH 35 30 SRL, SRH ISINK vs. VOL VCC = 12 V 25 ISOURCE (mA) ISINK (mA) 20 15 10 5 0 0 200 400 VOH (mV) www.vishay.com 600 800 25 20 15 10 5 0 0 VCC = 12 V 200 400 VOL (mV) 600 800 12 Document Number: 71815 S-41944--Rev. F, 18-Oct-04 SI9122 Vishay Siliconix TYPICAL CHARACTERISTICS tBBM vs. RBBM, VEP = 0 V 100 90 80 70 tBBM (ns) tBBM (ns) 60 50 40 30 20 25 30 35 RBBM (kW) 40 45 15 25 30 35 RBBM (kW) 40 45 tBBM3 tBBM2 VCC = 12 V tBBM1 55 tBBM4 45 tBBM3 35 tBBM2 65 VCC = 12 V tBBM vs. RBBM, VEP = 1.65 V tBBM4 tBBM1 25 tBBM1, 2 vs. Temperature, VEP = 0 V 80 tBBM1 = 13 V 60 tBBM1 = 12 V 55 50 tBBM1, 2 (ns) 45 40 40 tBBM2 = 10 V tBBM2 = 13 V 30 -50 -25 0 25 50 75 100 125 tBBM2 = 12 V 35 30 -50 tBBM1, 2 vs. Temperature, VEP = 1.65 V VCC = 12 V RBBM = 33 kW tBBM1 = 10 V tBBM1 = 12 tBBM1 = 13 70 tBBM1 = 10 V tBBM1, 2 (ns) 60 VCC = 12 V RBBM = 33 kW 50 tBBM2 = 10 V tBBM2 = 12 V tBBM2 = 13 V -25 0 25 50 75 100 125 Temperature (_C) Temperature (_C) tBBM3, 4 vs. Temperature, VEP = 0 V 70 65 60 tBBM13, 4 (ns) tBBM13, 4 (ns) 55 50 45 40 35 30 -50 tBBM3 = 10 V tBBM4 = 13 V tBBM4 = 12 V 60 50 40 VEP = 0 V RBBM = 33 kW tBBM4 = 10 V 70 80 tBBM3, 4 vs. Temperature, VEP = 1.65 V VEP = 1.65 V RBBM = 33 kW tBBM4 = 13 V tBBM4 = 12 V tBBM4 = 10 V tBBM3 = 13 V tBBM3 = 12 V tBBM3 = 10 V 30 20 -50 tBBM3 = 13 V tBBM3 = 12 V -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Temperature (_C) Document Number: 71815 S-41944--Rev. F, 18-Oct-04 Temperature (_C) www.vishay.com 13 SI9122 Vishay Siliconix TYPICAL CHARACTERISTICS tBBM1, 2 vs. VCC vs. VINDET 80 tBBM1 = 13 V tBBM1 = 12 V tBBM1 = 10 V tBBM1, 2 (ns) 55 tBBM1 = 13 V 50 tBBM1 = 12 V tBBM1 = 10 V 45 VEP = 1.65 V 40 tBBM2 = 13 V 35 3.5 tBBM2 = 10 V 4.5 5.5 VINDER (V) 6.5 7.5 tBBM2 = 12 V tBBM2 = 13 V tBBM1, 2 vs. VINDET vs. VCC 70 tBBM1, 2 (ns) 60 VEP = 0 V 50 tBBM2 = 10 V 40 tBBM2 = 12 V 30 3.5 4.5 5.5 VINDER (V) 6.5 7.5 tBBM3, 4 vs. VCC vs. VINDET 80 VEP = 0 V 70 tBBM4 = 10 V tBBM4 = 12 V tBBM13, 4 (ns) tBBM13, 4 (ns) 60 tBBM4 = 13 V 50 tBBM3 = 10 V 40 35 tBBM3 = 13 V 30 3.5 4.5 5.5 VINDER (V) 6.5 7.5 30 3.5 tBBM3 = 12 V 55 50 45 40 65 60 tBBM3, 4 vs. VINDET vs. VCC tBBM4 = 10 V tBBM4 = 12 V tBBM4 = 13 V VEP = 1.65 V tBBM3 = 10 V tBBM3 = 12 V tBBM3 = 13 V 4.5 5.5 VINDER (V) 6.5 7.5 60 50 I OUT, Duty Cycle %. V OUT IOUT vs. RLOAD (VIN = 7.2 V) Frequency 500 V ROSC (V), SRL, SRH, Duty Cycle(%) 50 45 40 35 30 25 20 15 10 5 0 1 Current Sense Duty Cycle vs. VCLCONT VINDET = 7.2 V 25_C Frequency D% 500 D% 40 400 400 Frequency (kHz) Frequency (kHz) 300 30 200 20 IOUT 10 0 0.0 100 VOUT 0 0.2 0.4 0.6 0.8 1.0 300 DSRL DDL 200 100 VROSC 0 2 3 VCLCONT (V) Document Number: 71815 S-41944--Rev. F, 18-Oct-04 4 5 RLOAD (W) www.vishay.com 14 SI9122 Vishay Siliconix TYPICAL WAVEFORMS Figure 7. Foldback Mode, RL = 0.02 W Figure 8. Normal Mode, RL = 0.1 W SRL 10 V/div SRL 10 V/div IOUT 5 A /div DL 10 V/div IOUT 5 A /div DL 5 V/div CS2 50 mV/div CS2 5 V/div 2 ms/div 2 ms/div Figure 9. VCC Ramp-Up Figure 10. VCL 2 V/div VEP 2 V/div Over Load Recovery--Minimum Overshoot VIN 2 V/div IOUT 10 A/div VOUT 2 V/div VCC 2 V/div 2 ms/div 200 ms/div Figure 11. Effective BBM--Measured On Secondary DH 5 V/div Figure 12. Drive Waveforms LX 20 V/div SRL 5 V/div DL 5 V/div SRH 2 V/div SRH 5 V/div SRL 2 V/div 500 ns/div 500 ns/div Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?71815. Document Number: 71815 S-41944--Rev. F, 18-Oct-04 www.vishay.com 15 Document Number: 71815 S-41944--Rev. F, 18-Oct-04 DEMONSTRATION BOARD SCHEMATIC DIAGRAM VCC P1 V IN 1 36 - 72 V P2 1 GND R3 470 kW R2 1 MW 2 R5 10 kW 2 R1 90 kW Q1 FMMT493 1 R27 1 MW Q2 FZT953 1 PNP 1 D1 BAS19 3 C1 1 mF 100 V 4 Q3 1, 2, 3 LX 5.6 7, 8 D2 10MQ100N VIN 3 3 Si4486EY R2 10 W VCC 2 nF 1 2 3 VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 BST DH LX DL PGND SRH SRL SS BBM CL_CONT 20 19 18 17 16 15 14 13 12 11 R8 5 kW R9 27 kW C14 4.7 nF 4 Q4 1, 2, 3 C8 0.1 mF 5.6 7, 8 D3 10MQ100N Work-In-Process www.vishay.com 1 2 3 P3 1 AGND JP1 SD EN C10 4.7 mF 16 V C30 200 - 800 pF R7 2 kW C9 C29 4 5 1 mF 10 V 470 pF 10 V 6 7 Si4486EY R6 35 kW C11 1000 pF 8 9 C12 15 pF 10 C13 4700 pF R10 2 kW R11 2 kW SRH R12 0.02 W 1/ W 2 Vishay Siliconix SRL VCC EP SI9122 15 SI9122 VCC 4 5.6 7, 8 VIN C2 1 mF 50 V + C1 15 mF 50 V + C4 15 mF 50 V T1 1, 2 4 5.6 7, 8 1, 2, 3 Q6 1, 2, 3 Q5 C17 0.1 mF Q7B Q7A 4 6 1 3 1 5 5 D8 BAS19 T3 LEP-9080 4 3.3 V 3.3 W R15 3.3 W D5 3, 4 EPC19 5.6 7, 8 1000 pF C16 1000 pF 30BQ040 D7 30BQ040 C22 47 mF 10 V C23 47 mF 10 V C24 47 mF 10 V C32 10 mF 6.3 V R17 NU 7, 8, 9 1, 2, 3 P4 3.3 V 1 15 A P5 3 4 6 D9 C21 0.047 mF 25 V 3 T2 6 5 3 EP7 4 3 D10 2 1 VCC EP BAV99 BAV99 2 1 1 Q10A C19 4.7 mF 16 V (1) 8 U03 LM7301 R19 3.9 kW LM4041CIM3-1.2 16 www.vishay.com Vishay Siliconix 2 Si3552DV 3 R16 10 W Si4886DY Si4886DY LX R13 15 W 800 mW C20 680 pF 100 V 7, 8 5, 6 D4 R14 11, 12 30BQ040 C15 9, 10 Work-In-Process Document Number: 71815 S-41944--Rev. F, 18-Oct-04 SRH SRL 1 1, 2, 3 Q7 D6 MBR0520 C33 0.1 mF C25 0.033 mF R26 5.6 kW R18 300 kW U3 AD820 6 (5) 7 5 C26 0.1 mF R20 20 kW (3) 3 2 (4) R25 2 kW 1 2 R21 51 W 1 3.3 V TP1 1 R22 33 kW C5 1 mF 50 V + C6 15 mF 50 V + C7 15 mF 50 V 4 Si4886DY 5.6 7, 8 1, 2, 3 Q8 4 2 C18 0.1 mF Si4886DY Q10B + - 1 4 (2) R23 18.6 kW P6 1 PGND P7 1 C27 C28 1000 pF 0.1 mF 3 Si3552DV 5 6 5 R24 1 MW U2 MOC207 PGND 1 2 7 C34, 0.1 mF |
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